Symmetrical Digital Dividers
These digital divider circuits permit the division of a frequency by odd integers (three, five and seven illustrated) while maintaining an output with a nearly-perfect 50% duty cycle square wave. This symmetry is useful in music applications where square waves may be filtered efficiently to extract the fundamental sine wave, with, for example, switched capacitor or continuous low-pass filters. The first example's waveforms (divide by three) illustrates the basic technique of deriving appropriate positive-edge clocking transitions by utilizing an exclusive-or gate preceding the first flip-flop (U1A). The very-short transitions at the output of U1A correspond to the time of propagation through the two flip-flops and the gate. A supply of +5 volts is indicated, although the CMOS devices shown operate within a range of +3 to +15 volts. The maximum recommended clock rate is 3.5MHz for a +5 volt supply. For applications requiring higher speeds, the circuit is readily adaptable to a number of other devices such as those using the HCMOS or bipolar Schottky process.
December 11, 2012
Text and image ©2012 by Arthur Harrison
Source documents dated May 1, 1997
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